This invention relates to a phase locked loop circuit which stabilizes an oscillation frequency of the oscillator utilizing the super high frequency diode such as a Gunn diode or an IMPATT diode by the PLL method using a source lock counter EIP578B made by EIP.
As shown in FIG. 1, the Josephson junction array voltage standard is obtained as follows:
The Josephson array 2 is put in a liquid helium container 1, to which an electromagnetic wave of millimeter wave is applied from an oscillator (Gunn oscillator) 11 using a Gunn diode, and in consequence, a voltage determined by the frequency of the millimeter wave thereof is generated which is the Josephson array voltage standard.
The oscillation frequency of the Gunn oscillator is stabilized by a phase locked loop circuit. The phase locked loop circuit, as shown in FIG. 1, is designed in such a way that the oscillation output of the Gunn diode 11 is supplied, through a directional coupler 3, to a source lock counter 12, and the output of the source lock counter 12 is, through a driver circuit 21, supplied to the Gunn oscillator 11 for the negative feedback control of the oscillator frequency of the Gunn oscillator 11. The EIP578B made by EIP is the only device commercially available as a source lock counter 12 to be used in the phase locked loop circuit for the high frequency (millimeter wave) oscillator described above, and the EIP578B is normally used, as the source lock counter 12, in the phase locked loop circuit for the Gunn oscillator for the conventional Josephson junction array voltage standard.
The source lock counter 12, EIP578B, is arranged as shown in FIG. 1. Namely, the oscillation output of the Gunn oscillator 11 is supplied to a frequency converter 13 in the source lock counter 12, and the oscillation output of a local oscillator 14 is frequency multiplied at a frequency multiplier circuit 15 the output of which is supplied to the frequency converter 13, in which the oscillation output from the Gunn oscillator 11 is converted to an intermediate frequency signal. The oscillation output converted to the intermediate frequency is supplied to a phase comparator 16 in which its phase is compared with a reference signal from a reference signal source 17. The output of the phase comparator is attenuated in a loop attenuator 18, and is supplied to a driver circuit 21 through a loop filter 19 as an error signal. In order to make the error signal thereof zero, the oscillation frequency of the Gunn oscillator 11 is controlled by a feedback with the output of the driver circuit 21, and is kept constant based on the reference signal from the reference signal source 17.
A time base 22 with an atomic frequency standard such as a rubidium (Rb) frequency standard supplies a reference clock RCK to the source lock counter 12, and the source lock counter 12 functions based on the reference clock RCK. The oscillation output of the local oscillator 14 is made from the reference clock RCK, and likewise, the reference signal of the reference signal source 17 is also made from the reference clock RCK. The frequency of the reference signal is tunable externally, and a multiplying value n of the frequency multiplier 15 is also changeable externally.
Conventionally, a 3-terminal regulator 23 is used for the driver circuit 21 as shown in FIG. 2. A bias voltage of 15 V is supplied to the 3-terminal regulator via a bias terminal 24, and the output of the source lock counter 12 (the output from the loop filter 19) is supplied to an adjust terminal 25 of the 3-terminal regulator 23.
The phase lock signal (error signal) of a center voltage, 0 V, from the loop filter 19 is converted, at the 3-terminal regulator 23, to a signal of a center voltage, 10 V, being a center which is output from the output terminal 26 of the 3-terminal regulator 23, and then supplied to the Gunn oscillator 11. That is, the control signal for the Gunn oscillator 11 requires for example, 10 V, 200 mA for the center frequency of 94 HGz, which is obtained at the driver circuit 21 from the signal of zero center voltage from the loop filter 19. As mentioned above, the voltage of the control signal for the Gunn oscillator 11 is high, and the current is also large, so that the 3-terminal regulator 23 often used for an adjustment (stabilization) of the power supply has been conventionally used as the driver circuit 21.
FIG. 3 shows a Bode diagram where curves 4 and 5 respectively represent gain characteristic and phase characteristic of the source lock counter 12 of EIP578B (hereinafter referred to as EIP source lock counter) the bandwidth of which is selected to be 10 KHz. When a GMR 3-terminal regulator made by Millitech is used for the driver circuit 21, the compound bode diagrams, for the overall gain and phase characteristics of the GMR 3-terminal regulator and the EIP source lock counter become as shown by curves 6 and 7 in FIG. 3, respectively. It is seen from the curves in FIG. 3 that when the 3-terminal regulator is used for the driver circuit 21, the slope of curve 6 becomes slightly steeper at around 10 KHz and the gain drops comparatively steeply above approximately 10 KHz. In addition, the delay of a phase develops compared to the frequency response characteristic for a phase of the EIP source lock counter alone. The phase delay becomes larger as a frequency becomes higher. The phase delay is approximately 150.degree. at and above 10 KHz, and a phase allowance is only about 30.degree..
Concerning a phase locked loop circuit (PLL), a damping factor .zeta. is defined (for example, FLOYDM, GARDNER "Phaselock Techniques", John Wily & Sons, 1966). It is known that the damping factor .zeta. is 0.707 for an optimum response. The frequency at a point where the frequency response curve of the loop filter makes a gain change at a lower frequency side is expressed as 1/.tau..sub.1, the frequency at a point where the frequency response curve of the loop filter makes a gain change at a higher frequency side is expressed as 1/.sub..tau..sub.2, and the phase detection gain factor and the control gain of the voltage controlled oscillator is expressed as Kd and Ko, respectively. The damping factor .zeta. when an active filter is used, in a secondary response loop, as a loop filter, will be defined as expressed in the following equation. ##EQU1##
The phase detection gain factor Kd of the EIP source lock counter 12 is 8.75 V/.pi. rad, and the values of loop filter .tau..sub.1 and .tau..sub.2 are respectively 1/30 sec. and 1/10.sup.4. The voltage control gain Ko in response to a frequency of the Gunn oscillator 11 can be expressed as 1.68.times.10.sup.8 .times.2.pi. (rad/sec)/V, then the damping factor .zeta. of the phase locked loop circuit shown in FIG. 1 is 4.7, which proves that it is significantly greater than the optimum value of 0.707.
Therefore, it is required to make the damping factor smaller, and it is conceivable, in accordance with the conventional technology, to optimize the damping factor by normally selecting the appropriate values for .tau..sub.1, and .tau..sub.2 of the loop filter. However, on the premise that the EIP source lock counter commercially available in the market is selected from an economical view point, it is difficult to change the values of .tau..sub.1 and .tau..sub.2 of the loop filter.
As described above, since the 3-terminal regulator is used in the phase locked loop circuit for the Gunn oscillator 11, and the overall characteristic is inferior to the characteristic of the EIP source lock counter alone, and the damping factor .zeta. is significantly larger than the optimum value, the frequency stability attained is approximately only 5.times.10.sup.-8 when a frequency deviation develops to a degree as indicated in FIG. 4. FIG. 4 is based on the 3-terminal regulator made by Millitech as described above and the Gunn oscillator 11 is GDM-10-4-18H, made by Millitech.
The objective of this invention herein is to offer the phase locked loop circuit for a SHF diode oscillator with higher frequency stability than conventional ones, using the EIP source lock counter.